| 摘要 |
A zero thermal budget process for the manufacturing of a MOS-technology vertical power device (such as a MOSFET or a IGBT) comprises the steps of: forming a conductive Insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (3) of a first conductivity type; selectively removing the insulated gate layer (8) from selected portions of the semiconductor material layer (3) surface; selectively implanting a first dopant of a second conductivity type into said selected portions of the semiconductor material layer (3), the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, heavily doped regions (5) substantially aligned with the edges of the insulated gate layer (8); selectively implanting a second dopant of the second conductivity type along directions tilted of prescribed angles ( alpha 1, alpha 2) with respect to a direction orthogonal to the semiconductor material layer (3) surface, the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, lightly doped channel regions (6) extending under the insulated gate layer (8); selectively implanting a heavy dose of a third dopant of a first conductivity type into the heavily doped regions (5), to form source regions (7) substantially aligned with the edges of the insulated gate layer (8). <IMAGE> |
