| 摘要 |
<p>An inexpensive single-chip integrated DRAM memory system having a high density and large bandwidth is provided comprising a DRAM array 10 having a plurality of pipelined stages 12, a control logic circuit 11 for controlling said DRAM array 10, and buffer means 13 integrated onto said chip for storing data being fetched from said DRAM array. The DRAM array and said control logic and said buffer means are all integrated onto one and the same substrate 1, wherein said control logic 11 generates a control signal for controlling operations taking place in said plurality of pipelined stages and the final stage of said pipeline 12 inputs/outputs data from said buffer means 13 in a burst mode. <IMAGE></p> |
