发明名称 |
Data communication system |
摘要 |
In order to combine an ARQ system and an FEC system, an error correction code is inserted between an error detection code for a variable-length ARQ frame and a frame boundary flag pattern. Information to be transmitted is divided into blocks having a suitable length by a block divider in accordance with a line quality judged by a line quality judger, and then subjected to a framing operation by an information frame preparer. The information subjected to the framing operation is attached with a CRC code by a CRC code generation/application circuit, subjected by a zero insertion circuit to an insertion of a suitable number of zero bits therein to provide a distinguished frame boundary with a flag, and the transmitted.
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申请公布号 |
US5638384(A) |
申请公布日期 |
1997.06.10 |
申请号 |
US19960614261 |
申请日期 |
1996.03.12 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
HAYASHI, KATSUHIKO;TATEISHI, TORU;MURANO, KATSUMI;AOKI, TAKAYASU;SATO, HIROAKI |
分类号 |
H04L1/00;H04L1/18;H04N1/32;H04N1/333;(IPC1-7):H03M13/00 |
主分类号 |
H04L1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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