发明名称 GENERATION OF ADDRESS SIGNAL AND DATA SIGNAL TO SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is decreased in the simultaneously switching noises of an address signal and a data signal. SOLUTION: A first memory bank (101) and a second memory back (102) are alternately accessed in time division. To access the first memory back, the address signal or the data signal is outputted to the first memory bank and simultaneously therewith, an inversion address signal and inversion data signal are outputted to the second memory bank. As a result, the currents flowing to positive and negative power sources are made alternately reverse symmetrical in the two memory banks and, therefore, the simultaneous switching noises are decreased.
申请公布号 JPH09153281(A) 申请公布日期 1997.06.10
申请号 JP19950311946 申请日期 1995.11.30
申请人 HITACHI LTD 发明人 TANAKA KATSUYA;KATO TAKESHI
分类号 G11C11/413;G06F11/00;G11C11/401 主分类号 G11C11/413
代理机构 代理人
主权项
地址