| 摘要 |
A pixel matrix filter includes n input buses to receive pixels of n successive columns of the matrix; n delay circuits respectively receiving the pixels from the n input buses, each of these delay circuits introducing a delay of one column, whereby 2n pixels are simultaneously transmitted to the outputs of the n delay circuits and to the n input buses, successively; and n adders connected at least so that the i-th adder receives the i-th of the 2n pixels at a first input and the (i+1)th of the 2n pixels at a second input.
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