发明名称 PLL CIRCUIT, SIGNAL PROCESSOR AND INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the number of external parts in the case of catching a 1st input, whose frequency is different for each frequency mode while keeping optimum transient response characteristics and stability for each frequency. SOLUTION: A gain (KIC) of 1st phase comparing means 2 at a 1st phase locked loop(PLL) circuit part 22 and equivalent serial resistance (RLPF) of active filtering means 25 for generating a 1st control input S17 corresponding to the compared result of 1st phase comparing means 2 and applying that input to a 1st voltage controlled oscillating means 3 are controlled by a control output S13 generated by a 2nd PLL circuit part 23, to which only one filtering means 31 is connected, corresponding to the frequency of 1st input S11.
申请公布号 JPH09153795(A) 申请公布日期 1997.06.10
申请号 JP19950334012 申请日期 1995.11.28
申请人 SONY CORP 发明人 AKABOSHI HIROYUKI
分类号 H03L7/093;H03L7/087 主分类号 H03L7/093
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