发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To optimize current consumption by changing a charging/discharging current during pulling-in corresponding to the level of phase error of comparing signal by shortening the pull-in [phase locked loop(PLL) stabilizing) time of charge pump circuit and suppressing jitter after lock as well. SOLUTION: This circuit is provided with a current source control circuit 9 with which the synchronism/asynchronism of input to a phase comparator 3 is discriminated by a synchronism discriminating part 18 and the value corresponding to the level of phase error of phase compared output is counted by a counter circuit 19, and a charge pump circuit 4 equipped with a switching control circuit 15 for inputting this compared output and a current source 17 provided with current supply parts I2-I5 to be weighted and controlled by the output of circuit 19 f in addition to an ordinary current I1 and a current mirror circuit 16 for converting the current of current source 17 to a charging/ discharging current I6 or I7 of control circuit 15. Then, a capacitor C1 of output terminal 13 is charged/discharged by the optimum charging/discharging current and after high-speed pull-in or jitter suppression is balanced, current consumption is optimized.
申请公布号 JPH09153796(A) 申请公布日期 1997.06.10
申请号 JP19950311247 申请日期 1995.11.29
申请人 NEC CORP 发明人 NISHIKAWA MASATO
分类号 H03L7/093;H03L7/089;H03L7/095;H03L7/107 主分类号 H03L7/093
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