GENERATING METHOD FOR POWER-ON RESET SIGNAL AND POWER-ON RESET CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a power-on reset circuit which can be contributed to the miniaturization of semiconductor integrated circuit device. SOLUTION: A PMOS transistor 1 is connected with an NMOS transistor 12. The PMOS transistor 11 is connected through a power source on switch 14 to a battery 15. The PMOS transistor 11 and NMOS transistor 12 input pulse signals from a pulse oscillator (OSC) circuit 16. The PMOS transistor 11 is connected through a diode 17 to a 2nd external terminal 18. The PMOS transistor 11 and NMOS transistor 12 are connected to a 3rd external terminal 19. A capacitor 20 is externally connected to the external terminals 18 and 19. An inverter 21 is connected to the external terminal 19 (node N2). The inverter 21 inputs a voltage VN2 of node N2 and outputs a power-on reset signal R.