发明名称 DIGITAL SYNCHRONOUS LOOP
摘要 PROBLEM TO BE SOLVED: To synchronize an inputted digital signal with a reference digital signal without using a voltage controlled oscillator by using a digital counter, a register and an arithmetic and logic circuit. SOLUTION: Counter clock controllers 10 and 11 input a clock signal and a zero cross signal to generate a counter clock signal to enable counters 20 and 21 to count. A data transmission controller 30 controls counted data to be transmitted and data transmission parts 40 and 41 transmit this data to a next stage. An N-bit parallel full adder 70 adds the output of the complement conversion part 50 and a reference digital signal from the N-bit register 60 to each other. The N-bit register 60 is provided with a reference speed. An N-bit digital/analog converter 90 converts the digital output signal of a binary data conversion part 80 to an analog signal and outputs it. Then a filter 100 corrects the gain of the whole circuit to send to a charging pump.
申请公布号 JPH09153792(A) 申请公布日期 1997.06.10
申请号 JP19960266861 申请日期 1996.10.08
申请人 SAMSUNG ELECTRON CO LTD 发明人 TOU SHIMEI;RI SANYOU
分类号 G05B11/06;H02P6/06;H02P23/00;H02P29/00;H03L7/00;H03L7/06;H03L7/181;H04L7/033 主分类号 G05B11/06
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