Latch-up verification device

摘要

A latch-up verification device including a latch-up verifying portion (3) which automatically performs a latch-up verification upon a layout pattern specified by layout pattern data (D1) by using transistor information (D4) with back gate terminal information given from the layout pattern data (D1) as a function of connection between a source terminal of respective transistors having the same back gate terminal information and a well region including the transistors, whereby the automatic latch-up verification with a constant accuracy is performed upon a layout pattern of CMOS structure with greatly increased efficiency.