| 摘要 |
A P-type flip-flop, which selectively functions in a D-type flip-flop mode or latch mode depending on its clock signal input. The P-type flip-flop has an output changing states to follow its data input at a leading edge of its clock input, the output then does not change states for a period epsilon , and then the output changing states to match its data input after the period epsilon if a signal is received at its clock input having a period greater than epsilon . With a pulse applied at the clock input having a width less than epsilon , the P-type flip-flop is edge sensitive functioning similar to a D-type flip-flop. With a pulse with longer than epsilon applied to the clock input, the P-type flip-flop appears transparent similar to a latch.
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