发明名称 DELAY FLUCTUATION GENERATION CIRCUIT FOR ATM CELL
摘要 PROBLEM TO BE SOLVED: To output an inputted cell while providing desired delay fluctuation by controlling the read timing of an output cell outputted from a delay buffer corresponding to section signals for indicating the start and end of a delay amount. SOLUTION: A delay object cell 11 to be a delay addition object is written in the delay buffer 1 by the write signals 12a of a read/write control circuit 4 and simultaneously, a delay amount monitoring counter 2 is counted up by the write signals 12a. Also, the delay amount counter 2 is counted down by read signals 12b and the delay amount and a counter value are matched. A section counter 5 outputs sections for indicating the start and the end of each delay amount set in a comparator circuit 3 to the read/write control circuit 4. Then, the read/write control circuit 4 controls the read timing of the cell outputted from the delay buffer 1 corresponding to detection signals 13 from the comparator circuit 3 and the section signals 14 for indicating the start and end of the delay amount from the section counter 5.
申请公布号 JPH09149049(A) 申请公布日期 1997.06.06
申请号 JP19950331161 申请日期 1995.11.27
申请人 ANDO ELECTRIC CO LTD 发明人 KANEKO YOHEI;SHIBATA KENICHI
分类号 H04L7/08;H04L12/28;H04L12/875;H04L12/879;H04L12/885;H04L12/951;H04Q3/00 主分类号 H04L7/08
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