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发明名称
LOGICAL DELAY SIMULATION METHOD
摘要
申请公布号
JPH09146980(A)
申请公布日期
1997.06.06
申请号
JP19950303207
申请日期
1995.11.22
申请人
NEC CORP
发明人
WATABE YASUNORI
分类号
G06F17/50;(IPC1-7):G06F17/50
主分类号
G06F17/50
代理机构
代理人
主权项
地址
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