| 摘要 |
PROBLEM TO BE SOLVED: To provide the phase controlled loop system in which a clock is recovered with high precision even on the occurrence of fluctuation in a phase in the vicinity of a sampling frequency. SOLUTION: Every time a transmitter side count ϕin is received, a reception counter 11 reads a count ϕout and it is subtracted from the count ϕin at a subtractor 12 and its output (e) is given to a 1st attenuator 13, its output Δf1 is given to a 2nd attenuator 14, and also its output is given to an integration device 15 and an integration output Δf2 is obtained. On the other hand, the Δf1 is given to an adder 16 and added to an integration output Δf2 and the sum is given to a converter 17, in which the signal is converted into a voltage signal and fed to a voltage controlled oscillator 18. Thus, the voltage controlled oscillator 18 outputs a clock ϕout (fv) with a frequency in response to an output of the adder 16 as a receiver side clock and it is given to the reception counter 11, in which the count ϕout is sequentially updated. |
