发明名称 SYNCHRONIZING SIGNAL DECODING CIRCUIT IN FREQUENCY DIVISION MULTIPLEX SIGNAL RECEIVER
摘要 PROBLEM TO BE SOLVED: To extract effectively a synchronizing signal embeded in an orthogonal frequency division multiplex(OFDM) signal. SOLUTION: A sample synchronizing signal is decoded by a 1st PLL 46 whose loop characteristic is inverted every each symbol period. Then a prescribed frequency component for a transmission band obtained by the PLL 46 is obtained, a phase comparator circuit 47 applies synchronization detection of an input demodulation OFDM signal, and a 2nd PLL consisting of a phase comparator circuit 48, a low pass filter (LPF) 49, a voltage controlled oscillator (VCO) 50 and a frequency divider 51 decodes a synchronization detection output signal to obtain the symbol synchronizing signal. Thus, the symbol synchronization decoded correctly by the 2nd PLL is used to conduct inversion processing of the loop characteristic of the PLL 46.
申请公布号 JPH09149002(A) 申请公布日期 1997.06.06
申请号 JP19950300011 申请日期 1995.11.17
申请人 VICTOR CO OF JAPAN LTD 发明人 TAKAHASHI NOBUAKI;SAEKI TAKAAKI;TAKAHASHI SUSUMU
分类号 H04J11/00;H04L7/033 主分类号 H04J11/00
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