| 摘要 |
PROBLEM TO BE SOLVED: To generate an intricate pattern while reducing the scale of circuit and the size by providing a plurality of address count means, a plurality of edge generation means, and a memory means, etc. SOLUTION: An edge generating section 100 generates a pulse for set edge at a timing corresponding to a delay of set edge being set in a memory means 8. An edge generating section 200 generates a pulse for reset edge at a timing corresponding to a delay of reset edge being set in the means 8. Address of the means 8 at the time of reading out the timing data is provided from address counters 101, 201 for counting a reference clock. An output pulse generating means generates a pulse for setting the edge with a delayed pulse from the generating section 100 and resetting the edge with a delayed pulse from the generating section 200. An intricate pattern can be generated easily depending on the data being set in the means 8. |
