| 摘要 |
PROBLEM TO BE SOLVED: To obtain a multiplication pattern by returning the output of plural ALU circuits to which the output of a main register is input to the main register through a select circuit, and retiming the same through another select circuit controlled by a sequence circuit. SOLUTION: A system clock of a timing generating part 7 is divided into three parts by a frequency divider 8 to be fed to a main register 1, auxiliary registers 13, 23, 33, and retiming circuits 41, 42, 43. In synchronization with the above, signals are sent from the register 1 to ALU circuits 12, 22, 32, and the arithmetic results 12A. 22A, 32A are sen to circuits 41, 42, 43 for retiming in synchronization with a dividing clock and sequentially output from an output register 4 with delay of one period of a dividing clock by a select circuit 2 controlled by a sequence circuit 6. The arithmetic results 12A, 22A, 32a are simultaneously passed through the select circuit 2 and feedbacked to the register 1. In this arrangement, it is possible to generate a test pattern at high speed with a small number of parts. |
