发明名称 DIGITAL MULTIPLEX BROADCASTING RECEIVER
摘要 PROBLEM TO BE SOLVED: To prevent enlargement of hardware and the increase of the cost by eliminating a need of preparing a private de-multiplexer for each multiplex system. SOLUTION: A system clock reproducing part consists of hardware consisting of an address decoder 210, a counter 218, plural latch circuits 211, 212, 213, 214, and 215, and a gate circuit 217. The counter 218 counts the system clock, and a pulse generation circuit 216 generates a timing signal for load of time information to the counter 218 and generates a timing signal for latch or the output value of the counter 218, and the multiplex system of a received broadcasting signal is discriminated by the CPU of a demultiplexer, and a strobe signal whose period corresponds to the discriminated multiplex system is given to the pulse generation circuit 216 to switch the generation timings of these timing signals.
申请公布号 JPH09148995(A) 申请公布日期 1997.06.06
申请号 JP19950301462 申请日期 1995.11.20
申请人 TOSHIBA CORP 发明人 KOSHIRO NATSUKI;SAKAMOTO NORIYA;YAMADA MASAHIRO
分类号 H04N19/42;H04B1/16;H04H20/00;H04H20/28;H04H20/44;H04H40/18;H04N7/08;H04N7/081;H04N7/24;H04N19/00;H04N19/423;H04N19/65;H04N19/70;H04N19/89 主分类号 H04N19/42
代理机构 代理人
主权项
地址