发明名称 A METHOD FOR REDUCING TRANSIENTS IN A CLOCK SIGNAL GENERATING SYSTEM
摘要 <p>The present invention relates to methods for reducing transients in a redundant clock system forming part of a switch in a telecommunication network. In general, the transients, normally in the form of phase steps, are caused by reconfigurations in the clock system. Examples of reconfigurations are an inclusion or an exclusion of a redundant clock generating circuit, referred to as a plane, or an activation of a network synchronization. In accordance with a general inventive concept, these transients are eliminated by successively adding an increment to a variable representative of a physical quantity in the clock generating system. In the case of an inclusion of a plane or an activation of the network synchronization, a positive increment is successively added to the gain of an amplifier. In the case of an exclusion of a plane, an increment is successively added to a phase difference representing signal.</p>
申请公布号 WO1997020410(A1) 申请公布日期 1997.06.05
申请号 SE1996001318 申请日期 1996.10.16
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址