| 摘要 |
The memory has word and bit lines and memory cells in silicon substrate, each with a MOS selection transistor and buried capacitor. The manufacturing starts with forming a chessboard pattern in minimum photostructure on the substrate, followed by anisotropic groove etching of chessboard parts not masked. Then the memory cells insulated by field oxide regions. The insulation is realised by silicon removing and substrate reducing oxidation of the quadratic mesas remained after the groove etching. Then, the quadratic, oxidised groove bottoms between the Si mesas in the chessboard pattern are exposed, followed by filling of the grooves by selective Si epitaxy.
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