| 摘要 |
<p>A memory subsystem 20 including a first memory bank 200a, having an array 201a of memory cells, a row decoder 202a for selecting a row in array 201a and a column decoder 204a for selecting at least one column in array 201b. Memory subsystem 20 also includes a second memory bank 200b including an array 201b of memory cells, a row decoder 202b for selecting a row in array 201b and a column decoder for selecting at least one column in array 201b. Address control circuitry 205, 206, 207 is included for presenting a first set of address bits to row decoder 202a of first bank 200a and the column decoder 204b of second bank 200b. Address control circuitry 205, 206, 207 further present a second set of address bits to column decoder 204a of first bank 200a and row decoder 204b of second bank 200b. <IMAGE></p> |
