发明名称 Programmable time delay in or relating to semiconductor memories
摘要 <p>Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (310-31n, 320-32n, 330-33n, 340-34n) coupled thereto which, in response to a control signal (b0-bn) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b0-bn) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (470-47n) and the capacitors (530-53n), respectively, are coupled in a capacitance charging circuit (470-47n, 43; 52, 530-53n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus. By coupling the apparatus in a ring configuration (Fig. 6), a counter unit (63), counting the number of signal delays through the delay apparatus (61) can lengthen the programmed time delay. <IMAGE></p>
申请公布号 EP0777232(A2) 申请公布日期 1997.06.04
申请号 EP19960118945 申请日期 1996.11.27
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 CLINE, DANNY R.;HII, KUONG HUA
分类号 G11C11/407;G11C7/22;G11C8/18;H03K5/13;(IPC1-7):G11C7/00;G11C8/00 主分类号 G11C11/407
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