| 摘要 |
Computers are frequently provided with cache systems to facilitate processor access to data, such systems serving to temporarily store selected data blocks read from a mass storage subsystem. In the present cache system, a portion (19) of system memory (11) is organised as cache memory, and a cache manager (30) is provided that exists separately of the processor (10) and system memory (11). Thus, in one embodiment the cache manager (30) interfaces with a peripheral bus (15) to which the mass storage subsystem (16, 17) is also connected. When the computer operating system (18) wishes to read a particular data block, it issues a request over the computer bus system to the cache manager (30) which, if the block is currently held in the cache (19), returns the cache address of that block. If the requested block is not in the cache, the cache manager (30) initiates the transfer of the block from the mass storage peripheral (16, 17) to the cache memory (19). The actual data block transfer may be performed under the control of the operating system (18) or, if the mass storage subsystem (16, 17) is DMA capable, by the mass storage subsystem itself. <IMAGE> |
