| 摘要 |
The clock generator in the net synchronization(10-1), after generating 32.768(MHZ) system basic clock, transmits the clock by using similar ECL differential level driver to the transmission line. After system basic clock is transmitted, central data link(20-1) receives the clock, using similar ECL differential level receiver, multiplies the clock (32.678(MHZ)), applying phase synchronous 100p method, to the system clock 65.536(MHZ) and inputs to the central data link device(22). The central data link(22) transmits and receives data with the locked data link system and realizes synchronization with the whole network.
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