发明名称 Read and writable data bus particularly for programmable logic devices
摘要 A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.
申请公布号 US5635851(A) 申请公布日期 1997.06.03
申请号 US19960595608 申请日期 1996.02.02
申请人 发明人
分类号 H03K17/687;H03K17/693;H03K19/177;(IPC1-7):H03K19/177 主分类号 H03K17/687
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