IMPROVEMENTS IN OR RELATING TO REAL-TIME PIPELINE FAST FOURIER TRANSFORM PROCESSORS

摘要

A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-2<2> algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-2<2> algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.