| 摘要 |
<p>A floating gate memory device which includes control circuits (2, 3, 4) to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block (1). This invention includes repairing the cells by applying a repair pulse to the cell's bit line (10, 11) while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.</p> |
