DYNAMIC PHASE SELECTOR PHASE LOCKED LOOP CIRCUIT

摘要

A dynamic phase selector phase locked loop circuit (20) includes: an A/D converter (24) for receiving an input signal (22) to be sampled; a phase detection circuit (26) for determining the phase error between the input signal (22) and a clock signal; a clock circuit (30), responsive to the phase detection circuit (26), for providing the clock signal to the A/D converter for timing the sampling of the input signal (22); the clock circuit (30) including a delay circuit having a number of delay taps; and a phase selector circuit (42), responsive to the phase detection circuit (26) for initially gating (43) the clock signals to the A/D converter from the clock circuit (30), and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.