METHOD AND APPARATUS FOR CONDITIONALLY COMBINING BIT METRICS IN A VITERBI DECODER FOR DECODING A RECEIVED INFORMATION SIGNAL

摘要

Methods and apparatuses for evaluating expressions used, for example, in convolutional decoders are described. By arranging digital logic elements in a manner designed to minimize the number of additions performed while evaluating hypothetical bit sequences, decoder performance is improved. Bit metrics and combinations thereof are first determined and supplied to a multiplexor. The multiplexor can then be controlled to output the selected one of the bit metrics or combinations thereof which is to be added to an accumulated path metric.