发明名称 |
Method of manufacturing a MOS device having a base region with high breakdown resistance |
摘要 |
<p>An n<+> drain layer 2 and an n<-> layer 1 on n<+> drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n<-> layer 1. An n<+> source region 6 is formed in the surface portion of p-type base region 3. A p<+> region 5, deeper than n<+> source region 6 and shallower than p-type base region 3, partially overlaps n<+> source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n<+> source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n<-> layer 1 and n<+> source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p<+> region 5 and n<+> source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n<+> drain layer 2. A junction face 20 of p-type base region 3 and n<-> layer 1 has a finite radius of curvature such that the depth from the surface of p<+> region 5 to junction face 20 is deepest beneath the center of p<+> region 5. <IMAGE></p> |
申请公布号 |
EP0776048(A2) |
申请公布日期 |
1997.05.28 |
申请号 |
EP19960118626 |
申请日期 |
1996.11.20 |
申请人 |
FUJI ELECTRIC CO., LTD. |
发明人 |
KOBAYASHI, TAKASHI;NISHIMURA, TAKEYOSHI;FUJIHIRA, TATSUHIKO |
分类号 |
H01L21/336;H01L29/06;H01L29/10;H01L29/739;H01L29/78;(IPC1-7):H01L29/78 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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