摘要 |
<p>In an oversampling digital-to-analog converter, an input 16-bit word digital signal is oversampled and quantized by a delta-sigma modulator into one of discrete values of +1, 0 and -1. A leaky integrator is coupled between the input and output terminals of an operational amplifier. A capacitor is charged by drawing a unit charge from a reference voltage source during a first half of the sample period of the +1 discrete value and discharged by injecting a unit charge to the input terminal of the operational amplifier during a second half of the sample period of the +1 discrete value. The capacitor is discharged during a first half of the sample period of the -1 discrete value and charged by drawing a unit charge from the input terminal of the operational amplifier during a second half of the sample period of the -1 discrete value. During the sample period of the 0 discrete value, the capacitor maintains a condition that occurs thereon during the second half of the sample period of either of the +1 or -1 discrete value. <IMAGE></p> |