Instruction decoder utilizing a low power PLA that powers up both AND and OR planes only when successful instruction fetch signal is provided

摘要

Disclosed is a programmable logic array (PLA), comprising an AND plane comprising a plurality of input lines and a plurality of product term lines crossing the input lines, an OR plane comprising the product term lines and a plurality of output lines crossing the product term lines, a power source VDD providing an electrical power to the AND and OR planes, and control line for controlling the supply of the electric power to the AND and OR planes, wherein the electrical power from the power source VDD is provided to the PLA when a signal indicating the use of the PLA is provided to the control line, and the supply of the electrical power from the power source VDD to the PLA is stopped on receipt of a signal designating that the PLA is in the unused state. In addition, various data processing systems incorporating the PLA are disclosed.