| 摘要 |
A logic synthesis method uses a two-dimensional sizing progression for selecting gates from a cell library in designing an integrated circuit. The drive load and desired performance for each logic gate in a functional configuration for the integrated circuit may be determined. The device configuration or gate to implement the logic gate may be selected from a cell library. The selected gate has a drive load range encompassing the determined drive load and achieves a desired performance target for the logic gate. A two-dimensional sizing progression may be used to help minimize layout area, power consumption, and performance loss in implementing BiNMOS gates.
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