| 摘要 |
<p>PROBLEM TO BE SOLVED: To generate clock signals with varied phases stably by providing a 1st clock generator and a 2nd clock generator generating inverted clock signals and delaying outputs of them. SOLUTION: A clock signal received from a clock input terminal 1 is fed to a counter 5 noninvertingly via a buffer 3 and inverted by a buffer 4 as a clock with a phase shift by 180 deg., and the inverted clock signal is fed to a counter 6. The counter 5 provides an output of a higher order bit (MSB) in two bits. For example, 2 bits in a binary system are '00', '01', '10', '11' (cyclic codes), then the MSB denotes 0, 0, 1, 1. Then an output of 1/4 frequency division of the received clock is obtained. The counter 6 provides an output of a 2nd smaller bit in 3-bit signals (2nd bit from the LSB). Then the buffer 3 and the buffer 5 with inverter generate noninverting and inverting clock signals respectively, each clock is delayed at a D FF by, e.g. 45 deg. each to obtain constant phase clock signals equal to a horizontal synchronizing signal.</p> |
