发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent lock-in near the upper limit or lower limit value of control frequency band by selecting a coefficient so as to position a clock output at the central part of multiplication control frequency band when off-lock is generated. SOLUTION: Assuming that off-lock is generated by fluctuating a clock frequency to fn from the state of locking in a coefficient set value at Qn, all the coefficients enabling lock-in are detected by a scanning operation and among the plural detected coefficients, the central coefficient is decided as a set value. Namely, for the clock frequency fn, lock-in control (pulling of frequency fn) can be performed to the coefficients from Qn+2 to Qn+10. In that case, the central coefficient Qn+6 is selected as the set value. Thus, the condition of lock-in at the upper limit value or lower limit value can be avoided and the conventional instable lock-in state can be avoided.
申请公布号 JPH09139863(A) 申请公布日期 1997.05.27
申请号 JP19950296726 申请日期 1995.11.15
申请人 FUJITSU GENERAL LTD 发明人 ISHII HIROBUMI
分类号 H04N5/06;H03L7/08;H03L7/10;H04N5/04 主分类号 H04N5/06
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