| 摘要 |
An array of programmable interconnect cells, each cell having a floating gate as the gate of an MOS switch transistor which programmably connect or disconnects nodes, is used in an FPGA. The floating gate of each cell, which is capacitively coupled to a control gate, is programmed by Fowler-Nordheim tunneling through an tunneling oxide above a programming/erase line in the integrated circuit substrate. Contiguous and parallel to the programming/erase line is at least one tunneling control line which forms a PN junction in close proximity to the programming/erase line region under the tunneling oxide. Under a reverse bias, a deep charge depletion region is formed in the programming/erase line region to block tunneling. In this manner, a selected cell can be programmed/erased, while the non-selected cells are not.
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