| 摘要 |
A fabrication method that enables to realize a semiconductor integrated circuit device having capacitors, bipolar transistors and IGFETs at a lower fabrication cost and a higher fabrication yield than the case of the conventional ones. After a first patterned conductor film having contours of first capacitor electrodes and of base electrodes is formed, a first patterned insulator film is formed on the first capacitor electrodes to produce first dielectrics A second patterned conductor film having contours of second capacitor electrodes and of gate electrodes is then formed on the first capacitor electrodes and the gate insulators. A second patterned insulator film is formed on the second capacitor electrodes to produce second dielectrics. A third patterned conductor film having contours of third capacitor electrodes and of emitter electrodes is formed on the second dielectrics, the base regions and source/drain regions. Each capacitor has a multi-layer structure of the first capacitor electrode, the first dielectric, the second capacitor electrode the second dielectric, and the third capacitor electrode. Each bipolar transistor has the base electrode contacted with the base region and the emitter electrode contacted with the emitter region.
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