Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver

摘要

A phase-locked loop circuit comprising a received data counter (11) for counting received clock signals reproduced according to sent data count values output from a transmitter, a subtracter (12) for subtracting the output of the received data counter (11) from an entered sent data count value, first and second attenuators (13, 14) for attenuating the output of the subtracter (12), an integrator (15) for integrating the output of the second attenuator (14), an adder (16) for adding the output of the first attenuator (13) to the output of the integrator (15), a converter (17) for converting the output of the adder (16) into the corresponding voltage signal, and a voltage control oscillator (18) that is controlled by the output of the converter (17) and outputs a received clock signal to be supplied to the received data counter (11).