| 摘要 |
A digital signal processor is mainly configured by a parallel-processing unit, a plurality of memory portions and a micro-code producing portion. Each of the memory portions accompanies with an input circuit and an output circuit, while the parallel-processing unit contains a plurality of operating elements such as multipliers, adders and the like. An interconnection manner among the operating elements is changed responsive to the micro code so as to embody a desired configuration by which a desired parallel processing can be carried out. One of the micro codes is selected in accordance with an operational result of the parallel-processing unit, so that the micro code to be supplied to the parallel-processing unit can be changed by one sampling period. In accordance with the micro code, data is read from a desired memory portion so that the read data is supplied to a desired operating element, while the operational result obtained from each operating element is written into a desired memory portion. Preferably, the parallel-processing unit is configured by an arithmetic and logic unit (ALU) and/or a programmable logic array.
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