| 摘要 |
<p>PROBLEM TO BE SOLVED: To attain accurate data transmission in all clock timings. SOLUTION: A variable signal delay circuit 14 of the device delays a clock signal (a) to generate a delayed clock signal. The delayed clock signal is given to a latch circuit 13. Furthermore, a phase difference monitor circuit 15 monitors the phase difference between the delayed clock signal ad the clock signal (a) and monitors the phase difference between the delayed clock signal and a clock signal (b) to change a delay in the variable signal delay circuit 14 so that the phase difference is a preset phase difference. Thus, accurate data transmission is conducted without being limited by the phase difference between the clock signal (a) and a data signal B.</p> |
