发明名称 Integrated circuit input/output processor having improved timer capability
摘要 Referring to FIGS. 1 and 2, I/O control modules (IOCMs 25-29) have channels which communicate by way of timer buses (71, 72) and pin/status buses (75-77). Channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebase values from timebase channels (80, 81) by their respective timer bus (71, 72), so there is no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). Pin/status buses (75-77) allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Pin/status buses (75-77) and timer buses (71, 72) can be independently partitioned.
申请公布号 US5634045(A) 申请公布日期 1997.05.27
申请号 US19950555456 申请日期 1995.11.13
申请人 MOTOROLA, INC. 发明人 GOLER, VERNON B.;MILLER, GARY L.;RIVERA, DAVID
分类号 G06F13/12;G06F1/14;G06F9/48;G06F15/78;(IPC1-7):G06F13/40;G06F1/04 主分类号 G06F13/12
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