| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory in which chips can be reduced and access can be performed at a high speed. SOLUTION: Signal generating circuits 105-15d consisting of a latch circuit 301 and NAND gate 303, 305 are arranged at the center part of the surface of a semiconductor substrate 102 having enough space, each of them is connected to memory cell arrays 101a-101d by four signal lines. Only output drivers 107a-107d consisting of inverters 701, 703 and an NMOS transistors 705, 707 are arranged near output pads 109a-109d in which the layout area is limited, further, connected to corresponding signal generating circuits with pairs of signal lines 113a-113d transmitting a complementary data signal. |
