Apparatus for operating a microprocessor core and bus controller at a speed greater than the speed of a bus clock speed

摘要

A microprocessor that operates at the speed of the the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals for operations within the microprocessor and bus clock signals for data transfer operations on the bus. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses.