FLAG GENERATING CIRCUIT FOR ZERO-BIT RATE IN FIFO DEVICE

摘要

A circuit for generating a flag signal for a zero bit rate of a FIFO(First In First out) comprises a number of FIFOs(10,20) for making an irregular input bit stream to a regular bit stream; a sensor(40) for sensing an empty state of the FIFOs; and a flag signal generator for generating the flag signal in case that the empty state is sensed, and providing the flag signal to the system to which the output from the FIFOs is applied, so as to reset the system.