| 摘要 |
<p>A capacitively/coupled successive approximation analog-to-digital converter utilizes a capacitively coupled digital-to-analog converter (60) to generate a succession of voltages which are compared (54) to the input voltage (56) to be digitized. The capacitively coupled digital-to-analog converter (60) generates the required succession of analog voltage levels utilizing very low power in response to digital signals. A doubled-version processes differential inputs with improved common mode rejection.</p> |
