Semiconductor device capable of reducing a clock skew in a plurality of wiring pattern blocks.

摘要

In a semiconductor device including a clock driver which provides clock signals, a plurality of electronic elements which are operable in timed relation to the clock signals, provided are a plurality of lattice-shaped wiring blocks to which the electronic elements are connected and each of which has a center portion, and an interconnecting wiring pattern connected to the center portion. The interconnecting wiring pattern connects the clock driver with the center portion of each lattice-shaped wiring block so that a distance between the clock driver and each center portion is substantially equal to one another in the center portions.