| 摘要 |
A calibration circuit (40) for infrared detectors including a first circuit (72) for storing a value representing the level of a first output of each detector in response to the illumination of the detector by a first target. A second circuit (74) stores a value representing the responsivity of each detector in response to the illumination of the detector by the first target. A third circuit (48), responsive to the first circuit (72), adjusts the level of the output of each detector in response to a second target and provides a level adjusted signal in response thereto. A fourth circuit (52), responsive to the second circuit (74), adjusts the responsivity of each detector in response to the second target and provides a responsivity adjusted signal in response thereto. A fifth circuit (58, 60, 62) feeds the output of the third circuit (48) back to the first circuit. (72). Finally, a sixth circuit (58, 60, 62) feeds the output of the fourth circuit (52) back to the second circuit (74). The invention performs level and responsivity equalization processing on the analog output of an Infrared Focal Plane Array (IRFPA), when in imaging mode and calculates the digital data for performing the equalization, when in calibration mode. Novel features of the invention include the use of close loop feedback in the calibration mode, the following ways: 1) The processed output is used to incrementally improve the digital level equalization (LE) or responsivity equalization (RE) value for each pixel. 2) The convergence target of the closed loop algorithm is programmable to any analog to digital converter (ADC) output code. 3) Data analysis of entire image frames of the processed ADC output is used set the value of the convergence target at each step of calibration (a secondary term of feedback). 4) Saturation logic guarantees stability of the loop and facilitates the detection of dead pixels.
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