发明名称 |
DRAM stack capacitor with ladder storage node |
摘要 |
A method, and resultant structure, is described for fabricating a DRAM (Dynamic Random Access Memory) cell having a stack capacitor with a ladder storage node, connected to a MOS (Metal Oxide Semiconductor) transistor with source and drain regions, to form a DRAM cell. A bottom electrode is connected to and extends up from the source region of the transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like manner. These step-like sides are formed by a repeated two-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. There is a capacitor dielectric over the bottom electrode. A top electrode is formed over the capacitor dielectric.
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申请公布号 |
US5631480(A) |
申请公布日期 |
1997.05.20 |
申请号 |
US19950494637 |
申请日期 |
1995.06.23 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE |
发明人 |
TSENG, HORNG-HUEI;LU, CHIH-YUAN |
分类号 |
H01L21/02;H01L21/8242;H01L27/108;(IPC1-7):H01L27/108 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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