| 摘要 |
A secondary cache memory system is disclosed for use in a portable computer that increases system performance while also conserving battery life. The secondary cache includes a cache controller for controlling the transfer to and from a cache memory, comprised of fast SRAM circuits. The cache controller includes a control and status register with at least three status bits to control power to the cache, and to insure that the data stored in the cache memory is coherent with system memory. A control and power management logic checks the contents of the control and status register, and monitors the activity level of the processor. When the processor is determined to be inactive, the control and power management logic turns off the cache by changing the state of a bit in the control and status register. Before doing so, however, the control and power management logic checks the status of a second bit in the control register to determine if some or all of the contents of the cache need to be flushed to system memory. During power up, the control and power management logic checks another status bit in the control register to determine if the contents of the cache is invalid, and if so, clears the cache.
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