| 摘要 |
A synchronous DRAM is disclosed. The DRAM comprises an input buffer, a memory cell array, an output buffer, a signal transfer circuit, first and second latch circuits, and a controller. The input buffer receives an operation control signal supplied externally. The memory cell array has a plurality of memory cells for storing data. The output buffer outputs a data signal read from the memory cells. The signal transfer circuit reads a data signal from one of the memory cells in accordance with the operation control signal from the input buffer, and sends this read data signal to the output buffer. The first and second latch circuits, provided between the input buffer and the output buffer, latch the associated input signals in response to a clock signal. The controller controls the latching operation of the second latch circuit by delaying the clock signal input to the second latch circuit for a period of time from when the first latch circuit receives input from the input buffer to when the read data signal arrives at the second latch circuit.
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